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VLSI Implementation of a High-Capacity Neural Network Associative Memory

Neural Information Processing Systems

In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation 3J.'-CMOSassociative memory (ECAM). The prototype programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via MOS transistors in this design. The prototype chipsub-threshold of performing one associative recall in 3 J.'S.is capable 1 ARCHITECTURE Previously (Chiueh, 1989), we have proposed a general model for correlation-based associative memories, which includes a variant of the Hopfield memory and highorder correlation memories as special cases. This new exponential correlation associative (ECAM) possesses a very large storage capacity, which scalesmemory exponentially with the length of memory patterns (Chiueh, 1988).


VLSI Implementation of a High-Capacity Neural Network Associative Memory

Neural Information Processing Systems

In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation associative memory (ECAM). The prototype 3J.'-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 J.'S.


VLSI Implementation of a High-Capacity Neural Network Associative Memory

Neural Information Processing Systems

In this paper we describe the VLSI design and testing of a high capacity associative memory which we call the exponential correlation associative memory (ECAM). The prototype 3J.'-CMOS programmable chip is capable of storing 32 memory patterns of 24 bits each. The high capacity of the ECAM is partly due to the use of special exponentiation neurons, which are implemented via sub-threshold MOS transistors in this design. The prototype chip is capable of performing one associative recall in 3 J.'S.